1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the device, more particularly to a capacitor cell structure.
2. Description of the Related Art
FIG. 6 is a sectional view showing a structure of a capacitor cell in a semiconductor device according to a conventional example. In FIG. 6, a silicon substrate 201 is provided with an active region 202. On the silicon substrate 201, a gate 200 is formed which is constructed of a gate oxide film 203, gate electrodes 204, 205 and a gate side wall/cap SiN film 206.
Furthermore, a flattened insulating film 207 is formed which surrounds the gate 200. On the insulating film 207, multilayer interlayer films 208, 209 and 210 are formed. In the insulating film 207 and the multilayer interlayer films 208, 209 and 210, contact holes are formed. In each contact hole, a poly-Si plug 211 and a W-plug 213 (and a barrier layer 212) are formed.
On the multilayer interlayer film 210, a barrier layer (a TiSi film or a TiAlN film) 214 and a lower electrode (an Ir film) 215 of a capacitor are formed so as to be connected to the W-plug 213. In consequence, the active region 202 is connected to the capacitor lower electrode 215 via the poly-Si plug 211, the W-plug 213 and the barrier layer 214.
Furthermore, on the capacitor lower electrode 215, a ferroelectric capacitor insulating film (Pb(Zr, Ti)O3) 216 and a capacitor upper electrode 217 are formed. On the capacitor upper electrode 217, an Al2O3 film 218 and an SiO2 film 219 are formed. The Al2O3 film 218 and the SiO2 film 219 function as a mask for processing the capacitor upper electrode 217, the capacitor insulating film 216, the capacitor lower electrode 215 and the barrier layer 214 by reactive ion etching (RIE).
When the capacitor is formed by the RIE processing, a capacitor cover film 220 and an interlayer insulating film 221 are formed so as to surround the capacitor. Furthermore, in the interlayer insulating film 221, a contact 222 and a wiring line 223 are formed so that they extend through the capacitor cover film 220, the second mask film 219 and the first mask film 218 to be connected to the capacitor upper electrode 217 and they electrically couple TE to TE between capacitor cells arranged adjacent to each other (a so-called dual damascene structure).
In addition, it is particularly to be noted that after the interlayer insulating film 221 is RIE-processed and an opening for the contact 222 and a groove for the wiring line 223 are formed, recovery annealing is performed in an oxygen atmosphere at 600 to 650° C. for about one hour to alleviate plasma damages in the capacitor insulating film 216.
In the above conventional capacitor structure, since the surface of the capacitor processed by the RIE process comes into contact with an interface between the upper electrode and the ferroelectric film, the ferroelectric film and an interface between the ferroelectric film and the lower electrode of the capacitor, the capacitor is largely damaged during the etching. Therefore, problems occur that a quantity of signals required for operating the device cannot be obtained, or the signals decrease and reliability of the device deteriorates.
Moreover, there is a problem that a fence is attached to the processed surface during the etching of the capacitor lower electrode, which is a cause for short-circuiting between the upper electrode and the lower electrode or increasing a leak current flowing through the capacitor. The reliability of the device deteriorates.
It is to be noted that in Jpn. Pat. Appln. KOKAI Publication No. 2004-342974, a semiconductor storage device is disclosed. The semiconductor storage device has a data storing capacity element including a lower electrode, a capacity insulating film constituted of a ferroelectric film or a highly dielectric film and an upper electrode successively formed on a semiconductor substrate provided with a transistor; an insulating barrier film to prevent diffusion of hydrogen into the capacity insulating film; a bit line formed on the insulating barrier film; and a bit line load capacity element including a load capacity lower electrode constituted of the lower electrode or an upper electrode, a load capacity insulating film constituted of an insulating barrier film, and a load capacity upper electrode constituted of a bit line.
In Jpn. Pat. Appln. KOKAI Publication No. 2004-311941, there is disclosed a flat plate type capacitor including a lower wiring line formed at a predetermined portion of a semiconductor substrate; a lower electrode electrically connected to the lower wiring line; a concave dielectric film formed in an upper portion of the lower electrode; a concave upper electrode which is larger than the lower electrode and which is formed in an upper portion of the dielectric film; a first upper wiring line electrically connected to the lower electrode; and a second upper wiring line connected to the upper electrode.